70 -- SHARCPAC MODULE W/XILINX FPGGA DIGITAL I/0 INTERFACE

Notice Date

October 13, 2000

Contracting Office

Commercial Acquisition Department, Bldg 11, Naval Undersea Warfare Center Division, Newport, Code 59, Simonpietri Dr., Newport, RI 02841-1708

ZIP Code

02841-1708

Solicitation Number

N66604-01-Q-0161

Response Due

October 27, 2000

Point of Contact

J. Whiteman, Contract Negotiator at (401) 832-1927; L. Brazil, Contracting Officer at (401) 832-1437; FAX (401) 832-4820

E-Mail Address

Jeanne Whiteman, Contract Negotiator (whitemanjy@npt.nuwc.navy.mil)

Description

The Naval Undersea Warfare Center Division Newport intends to award a Firm Fixed Price Contract on a Sole Source basis to Spectrum Signal Processing, 8201 Corporate Dr., Landover, MD 20785 for (36) thirty six SHARCPAC Modules w/Xilinx FPGA digital I/O Interface. These modules will be implemented to provide a digital interface to the Digital Signal Processor (DSP) Boards using the available onboard Field Programmable Gate Array (FPGA) chip as the Input/Output (I/O) port. The Government plans to issue a request for written quote to Spectrum Signal Processing using FAR Part 12 and FAR Part 13. The anticipated award date is 3 Nov 00. This action is being processed on a Sole Source basis due to the fact that these SHARCPAC modules have been designed and tested in the Digital Signal Processing system as a special-purpose plug-in module in the current East Coast Shallow Water Training Ranges (ECSWTR) Program. In order to maintain compatibility with existing modules, it is necessary to procure SHARCPAC modules from Spectrum Signal Processing who is the manufacturer and distributor of these modules. The SHARCPAC modules will be mounted on a custom, Naval Undersea Warfare Center developed carrier board and thus requires that all connections take place from the bottom of the module and be implemented on a single 4.5" x 3.1" card. The modules shall be configured with a minimum of one (1) Analog Device ADSP-21060 digital signal processor (DSP), operating at a minimum of 40 MHZ. The processor shall have a minimum of ten (10) independent DMA controllers, a 240 MByte/sec communication bandwidth and must meet a 120 MFLOPS CPU performance. The DSP chip must have at least 4MB of internal memory. The Modules shall provide a minimum of six (6) 40 MByte/sec link ports, two (2) 40Mbit/sec serial ports, Flag and IRQ signals for interface via the SHARCPAC connectors. The SHARCPAC module must include a Xilinx 4020E (or higher density) FPGA with a minimum of one hundred (100) TTL or CMOS configurable I/O pins. NOTE: These pins must be connectorized on the BOTTOM of the module so as to plug in directly onto the carrier board, or provide through-hole openings for user-selectable connectors. The Module connector height shall be 0.225 inches. Recommended connector for the SHARCPAC module (pin) is the Samtec surface mount connector TFM-145-02-S-D-LC. The maximum SHARCPAC module width (from the bottom of the module connector to maximum component height on top of the module) shall be 0.7 inches. The SHARCPAC module must operate on 5V power and consume no more than 10 watts. The module must operate at an ambient temperature between 0 degrees centigrade and 50 degrees centigrade. The SHARCPAC Module with the following exceptions to the SHARCPAC Module Specifications to allow SHARC booting from an external PROM (Programmable Read Only Memory): The LBOOT signal must be routed to J2 pin 34 and connected to a 10k ohm pull-up resistor. This will replace the ADDR23 signal. The EBOOT signal must be routed to J2 pin 36 and connected to a 10k ohm pull-down resistor. This will replace the ADDR24 signal. The BMS signal must be routed to J2 pin 128 and connected to a 10k ohm pull-up resistor. This will replace the ADDR26 signal. The vendor must also provide the following development software and emulation support: Software Library for module initialization from PROM, FLASH memory, or the host system. Delivery will be F.O.B. Destination, Newport, RI. This acquisition is 100% Set Aside for Small Business. Our department no longer issues solicitations or amendments in paper form. Instead, they may be accessed at our web site http://www.npt.nuwc.navy.mil/contract/. We also provide electronic access in our Bid Room. Estimated RFP release date: 10-20-00; NAICS Code: 334119.

Web Link

NAVAL UNDERSEA WARFARE CENTER DIVISION, NEWPORT (http://www.npt.nuwc.navy.mil/contract/)

Record

Loren Data Corp. 20001017/70SOL005.HTM (W-287 SN5042M2)