SPECIAL NOTICE
99 -- MULTIPLE-CHANNEL COHERENT DIGITIZER/DIGITAL SIGNAL PROCESSOR
- Notice Date
- 3/10/2004
- Notice Type
- Special Notice
- Contracting Office
- P.O. Box 190022, North Charleston SC 29419-9022
- ZIP Code
- 29419-9022
- Archive Date
- 4/9/2004
- Description
- SPAWAR System Center Charleston is soliticing a response from potential small business sources to provide the Government the following: Multi-Channel Coherent Digitizer/Digital Signal Processor, 8 Channel coherent signal processor architecture w/ modular and scaleable design, Modular ADC, FPGA, DSP design with high speed input/output data bus between modules. Provides up to 3 kinds of modules: 1) Quad ADC w/ FPGA, 2) Large FPGA (6+M gates) and 3) RISC processor w/ FPGA. Details of carrier board and each module listed below: Module Carrier Board, Quad ADC/FPGA module, Large FPGA module, RISC/FPGA module, See attached concept drawing. Inter-Module High Speed Input/Output (I/O) Channel Architecture using FPGA technology, 400 Mbytes/sec per channel transfer rates between modules, Up to 500K gates allowed for high speed data I/O, but prefer less. Inter-Module to Host Computer I/O Channel, Compatible with RS-232 or USB Interface For lower speed state machine communications between modules and host computer FPGA or RISC processor programming interface I/O, Full host computer access to any FPGA or RISC device via industry standard JTAG interface, See attached concept drawing. Shock & Vibration, Aiming at MIL-STD-810, It is understood that formal laboratory conformance tests will not be required, but good construction practice will be employed throughout. Operating Temperature Range, 0-60 degrees Centigrade, Humidity, 20-90% non-condensing, Deliverable Date, 6 Weeks ARO, Established Product Line Maturity, Existing commercial-off-the-shelf product listing and published costs, Warranted against defects, 1 year after delivery. Carrier Board for Modules, Size of Carrier Board, 12? x 9? x 1.5? (81 in3), See attached concept drawing Number of processing modules fitting on a single carrier board, Adequate module sites to populate board with 8 ADCs streaming data to 2 Large FPGAs and 4 Fixed Point RISC processors, See attached concept drawing. Module Form Factor, Commercial modular format is acceptable; e.g., PMC, TIMS, PC-104, etc., See attached concept drawing. Input Power, 9 ? 18 Vdc @ 300 Watt Maximum Capacity, See attached concept drawing. Weight, Maximum 72 oz , Fully populated 8 module carrier board. Module 1 - Quad Analog-to-Digital Converter (ADC)/FPGA Specifications, Number of Simultaneous Analog Input Signals, 4 Channels per module with capability to synchronize and lock ADC sampling clocks to same clock source to achieve a minimum of 8 locked ADC channels, Prefer scaleable design with modular sets of 4 analog-to-digital converters (ADC) per module with capacity up to 32 ADCs. Input Frequency Range, DC ? 42 MHz, Prefer up to 200 MHz. Sampling Rates, Variable up to 105 MS/s, Selectable Sampling Rates with multiple sampling rates preferred besides 2 units. Sample Bit Size, 14 bits, Monolithic design preferred. Sampling Jitter, 0.1 ps, ps = picoseconds Sampling Synchronization Variance between all 8 channels, 0.2 ps, Design must allow for distributed sampling clock in order to coherently lock all 8, but allow for up to 32 locked channels Minimum Spurious Free Dynamic Range @ 70 MHz Input Frequency, 89 dBc,. Minimum Multi-tone Spurious Free Dynamic Range, 100 dB, . Signal-to-Noise Ratio (SNR), 75 dB at 15 MHz input. 72 dB at 200 MHz input, Meets specification up to 105 MS/s sampling rates. Input Connectors/Impedance, 8 SMA @ 50 ohm, Adapter cables acceptable. Type of Analog Connection at ADC Input, Differential, Inter-Module High Speed I/O Channels, 2 Channels @ 400 Mbytes/sec per channel transfer rates, Based on 4 ADC channels of data plus 8% for I/O overhead. Field Programmable Gate Array (FPGA) Processor, One 1 million gate FPGA or larger, Xilinix XC2V1000 or XC2V2000, Due to large investments in Virtex-II based FPGA GFE source code, development tools, and training, other FPGA processors cannot be considered. Full user programmability of the FPGA, Full user access to FPGA via industry standard JTAG interface, Up to 50% capacities (500K gates) allowed for high speed data I/O, but prefer less. Size & Form Factor, 4 ADC chips and FPGA occupy 1 module sized card , FPGA for post ADC processing and high speed I/O. Power, Maximum 20W per channel module , Weight, Approximately 9 oz per module. Module 2 - Large FPGA Specifications, , Field Programmable Gate Array (FPGA) Processor, One 6 million gate FPGA or larger, Xilinx XC2V6000 or XC2V8000. Due to large investments in Virtex-II based FPGA GFE source code, development tools, and training, other FPGA processors cannot be considered. Additional off chip memory for FPGA data storage and transfer, 4 Mbytes of SRAM storage capacity w/ 36 Gb/s transfer rates, Full user programmability of the FPGA, Full user access to FPGA via industry standard JTAG interface, Up to 15% (1M gates) capacity allowed for high speed data I/O, but less is more favorable. Inter-Module High Speed I/O Channels, 4 Channels @ 400 Mbytes/sec transfer rates, Based on a 200 MHz clock rate over a 240 pin connector/channel Power, Maximum 20W per channel module, Weight, Approximately 9 oz per module. Module 3 - RISC/FPGA Specifications: Reduced Instruction Set Computer (RISC) Processor for Fixed Point State Machine processes, Single RISC DSP, Texas Instruments TMS320C6416 w/ a 600MHz clock and 6 MB of SRAM, DSP/RISC processor supports various user selectable functions from JTAG interface. FPGA for High Speed I/O, Single 2M gate FPGA, Xilinix XC2V2000, FPGA supports I/O requirements plus added capacity for various other user-defined functions. Full user programmability of the FPGA and RISC processors, Full user access to FPGA and DSP via industry standard JTAG interface, Up to 25% capacity of FPGA allowed for high-speed data I/O, but less is more favorable. Inter-Module High Speed I/O Channels, 2 Channels @ 400 Mbytes/sec transfer rates, Based on a 200 MHz clock rate over a 240 pin connector/channel. Power, Maximum 20W per channel module @ 12VDC, 120VAC/12VDC adapters shall be supplied. Weight, Approximately 9 oz per channel module. Support Software/Hardware, Drivers for carrier board and all 3 types of module cards, Drivers to access all three types of modules from 1 JTAG interface, Drivers work with Texas Instruments C6x Code Composer Studio 2.0 or later and Xilinx ISE Foundation Development Tools 6.2 using VHDL programming language. JTAG to Windows Computer Interface, JTAG to PCMCIA Interface Module with associated 2? cable, JTAG to USB would also be acceptable, but PCMICA interface typically has faster transfer rates. Example Software, Loading FPGAs and RISC Executable Binary Files, Software source code that demonstrates loading executable code to any of the 3 modules, high-speed data between modules, and data between modules and host Windows computer, Example works with Xilinx ISE Foundation Development Tool. Software Example, Inter-Module High Speed Data I/O, Software source code that demonstrates full 400Mbyte/s data transfer between any one of all 3 modules, Example works with Xilinx ISE Foundation Development Tool. Software Example, Quad ADC/FPGA module, Software source code that controls sampling rate and digitally adds gain to any of the 4 ADC data streams, Example works with Xilinx ISE Foundation Development Tool. Software Example, Large FPGA module, Software source code that reads in 4 ADC data streams via the high-speed bus and performs a 1024 point Radix 2 Fast Fourier Transform (FFT), Example works with Xilinx ISE Foundation Development Tool. Software Example, RISC/FPGA module, Software source code that reads in 4 1024 point FFT data streams via the high speed bus and sums each of the 4 point values and divides them by 4. The results are then sent out to the host Windows computer for display., Example works with Texas Instruments C6x Code Composer Studio and Xilinx ISE Foundation Development Tools. Shall have an established Product Line on the Market, commercial-off-the-shelf beam forming processing with modular design. This is only a request for information about commercial products matching the above generic requirements. If a satisfactory response is received, a solicitation may be issued. Firms are invited to submit appropriate documentation, literature, brochures, and references that support they possess the specification necessary to meet or exceed stated requirements. Responses shall be submitted to SPAWARSYSCEN, Charleston, ATTN: SUZANNE HUERTH, Code 734SH, (843) 281-5915, P.O. Box 190022, North Charleston, SC 29419-9022, or by electronic mail to suzanne.huerth@ navy.mil by COB 09 April 2004. (Request that name and size of firm be stated in subject line of e-mail message). Responses must include the following: 1) name and address of firm; (2) size of business, (3) ownership: Large, Small, Small Disadvantaged, 8(a), and/or Woman-Owned; (4) number of years in business; (5) technical capability; (6) affiliate information: parent corporation, joint venture partners, prime contractor (if potential sub) or subcontractors (if potential prime); (7) a list of customers covering the past 5 years; highlight relevant technical cability, contract number, contract type, dollar value for each customer reference, and customer point of contact with phone number. THIS IS A RERQUEST FOR INFORMATION AND PLANNING PURPOSES AND IS NOT TO BE CONSTRUED AS A COMMITMENT BY THE GOVERNMENT. THIS IS NOT A SOLICITATION ANNOUNCEMENT FOR PROPOSALS AND NO CONTRACT WILL BE AWARDED FROM THIS ANNOUNCEMENT. NO REIMBURSEMENT WILL BE MADE FOR ANY COSTS ASSOCIATED WITH PROVIDING INFORMATION IN RESPONSE TO THIS ANNOUNCEMENT AND ANY FOLLOW-UP INFORMATION REQUESTS. RESPONDENTS WILL NOT BE NOTIFIED OF THE RESULTS OF THE EVALUATION. RESPONDENTS DEEMED FULLY QUALIFIED WILL BE CONSIDERED IN ANY RESULTING SOLICITATION FOR THE REQUIREMENT. THE GOVERNMENT RESERVES THE RIGHT TO CONSIDER SET-ASIDE FOR SMALL BUSINESSES BASED ON RESPONSES HERETO. THE APPLICABLE NAIC CODE IS 334220 WITH A SIZE STANDARD OF 750 EMPLOYEES. CLOSING DATE FOR RESPONSES IS 9 APR 2004.
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- Record
- SN00542167-F 20040312/040310233253 (fbodaily.com)
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