SOLICITATION NOTICE
A -- X-BAND DIGITAL BEAMFORMING RECEIVER TECHNOLOGY, PART 1 OF 2
- Notice Date
- 1/7/2003
- Notice Type
- Solicitation Notice
- Contracting Office
- ESC/PKR, R&D Contracting Division, 104 Barksdale St., Hanscom AFB, MA 01731-1806
- ZIP Code
- 01731-1806
- Solicitation Number
- PRDA-AFRL/SNH-03-01
- Response Due
- 2/21/2003
- Archive Date
- 8/21/2003
- Point of Contact
- Richard Halloran, Contracting Specialist, 781-377-4981 Gino F. Cascieri, Contracting Officer, 781-377-2623
- E-Mail Address
-
Email your questions to Click Here to E-mail the POC
(richard.halloran@hanscom.af.mil)
- Small Business Set-Aside
- N/A
- Description
- This PRDA is being posted in two parts. This first part contains sections called SOLICITATION, BACKGROUND, PROGRAM DESCRIPTION, TECHNICAL GOALS, and TECHNICAL APPROACH. The second part, posted separately, contains sections called BASIS FOR AWARD, DELIVERABLES WILL INCLUDE, and PROPOSAL PREPARATION INSTRUCTIONS. SOLICITATION. Mr. David Curtis, AFRL/SNHA, Laboratory Program Manager, david.curtis@hanscom.afrl.af. mil, 781-377-2049, Dr. Stephen Hary, AFRL/SNRP, Technical Consultant, stephen.hary@wpafb .af.mil, 937-255-6127 x4175, and Mr. Gino Cascieri, ESC/PKR, Contracting Officer, gino. cascieri@hanscom.af.mil, 781-377-4981, representing the AFRL Sensors Directorate, Hanscom Research Site, located at Hanscom Air Force Base, are soliciting proposals for new and innovative solutions to digital beamforming receiver technology. This is a single-step, 45-day, Program Research and Development Announcement (PRDA) to solicit research and development proposals for the AFRL/SN X-Band Digital Beamforming Receiver program. BACKGROUND Digital beamforming (DBF) is a rapidly developing technology which is the most advanced approach to phased array antenna pattern control. When implemented at the array element level, DBF enables full utilization of the maximum number of degrees of freedom in the array. This can lead to significant improvements in beamforming of simultaneous multiple independent beams, adaptive pattern nulling, space-time adaptive processing (STAP), and direction finding (DF), compared to traditional analog array control techniques. Because of its flexibility, DBF may find use in a wide range of phased array antenna applications. One near-term application for subarray-level DBF is in large, relocatable ground-based phased arrays for Ballistic Missile Defense (BMD) and theater air defense. Mid-term DBF applications include conformal arrays for low profile aircraft such as Unmanned Air Vehicles (UAV), Unmanned Combat Air Vehicles (UCAV), and in next-generation manned airborne reconnaissance platforms. Sensors aboard these airborne platforms would typically support Airborne / Ground Moving Target Indication (AMTI / GMTI) radar and Synthetic Aperture Radar (SAR) for Intelligence, Surveillance and Reconnaissance (ISR) mission applications. Subarray-level DBF also applies to very large planar arrays for space-based radar, where very low power and extremely low mass density are key requirements for satellite applications. Today's state-of-the-art DBF phased arrays are primarily of laboratory prototype quality, and employ digital receivers only at the subarray-level. This is due to challenges both with RF receiver hardware, including reduction of size, mass, and DC power consumption, as well as digital challenges that include increasing ADC sampling rate, implementing digital sub-banding and digital time delays, and processing enormous data loads associated with DBF algorithms. Digital receiver (Rx) technology tailored for the DBF array application is a newly emerging avenue of research and development that will significantly impact architectural trends in DBF phased array antennas and enable accelerated implementation of DBF. DBF Rx technology will likely adopt many of the features found in today's state-of-the-art Multi-Function Radar (MFR) receivers and/or Electronic Warfare (EW) receivers. Currently, digital radar receivers include, but are not limited to the following features: RF receiver front-end for RF-to-IF or RF-to-baseband demodulation, Automatic Gain Control (AGC) for RF front-end protection against strong interfering signals, analog-to-digital converters (ADC) for bandpass or baseband sampling, and digital finite impulse response (FIR) filtering for decomposition of sampled signals into in-phase and quadrature (I/Q) components. DBF Rx technology requires all of these core digital Rx capabilities, plus many others which are essential for digital control and optimization of phased array antenna patterns. These include, but are not limited to the following: FIR digital filtering for DBF Rx channel equalization to enable wideband array-level channel-to-channel calibration; use of either digital sub-banding schemes such as multi-rate digital filtering or implementation of fractional sample digital time delays, to enable wideband beamforming and adaptive nulling; pulse compression and data reduction techniques for radar processing; programmability of bandwidth vs. resolution for MTI / SAR mission flexibility; novel data formatting schemes optimized for fast complex-valued channel-level digital processing; a high degree of built-in programmability for implementation of advanced algorithms for beamforming, channel filtering and sub-banding; module-level digital self-registration capabilities with respect to the system-level distribution and temporal aligning of digital clock and synchronization signals, coherent phasing of RF local oscillator (LO) signals, and array channel calibration RF pilot tones; and module-level self-assessment capabilities that monitor the overall in-situ performance of the DBF Rx array channel. The use of miniturized modular tile-like packaging concepts is also desired in order to advance the state-of-the-art of low-profile DBF phased array architectures that are both scalable and modular. Recent trends in DBF Rx technology development have utilized commercial off-the-shelf (COTS) standardized VME and VXI electronic mainframes and circuit boards which support a modular building-block approach to DBF system implementation. In many cases, however, it is desirable to implement DBF in a much smaller volume and with a much lower mass density. One concept now being explored by AFRL/SN is the layered integration of a planar digital signal processor architecture with a planar DBF phased array architecture, using modular tile-based DBF Rx technology in the interface between the array and processor layers. One potential benefit of this modular, scalable approach is the reuse of key electronic sub-systems across many different DBF arrays architectures. It is anticipated that the Air Force may achieve significant cost savings using modular DBF Rx components in scalable DBF phased array sensor architectures, with the most significant savings derived from reduced life-cycle system maintenance costs and multi-system amortization of non-recurring engineering costs of the modular array electronics. PROGRAM DESCRIPTION This solicitation is open only to companies headquartered within the United States of America. This effort shall not use or produce any classified information. This effort will have funding over a three (3) year performance period. The Air Force estimates its investment in this effort to be approximately equivalent to 10 man-years, fully burdened. The actual amount of labor will be less, assuming an approximate 60/40 spending ratio between manpower and all other costs. Since this is the first of potentially many related contractual efforts to come from the AFRL/SN X-Band Digital Beamforming Receiver Program, the vast majority of the technical output from this effort must be non-proprietary. This must be done to ensure that what is learned in this contractual effort may be freely utilized by the Air force to advance the technical base of the AFRL/SN X-Band Digital Beamforming Receiver Program, and to advance the state-of-the-art of DBF Rx technology in general. Outputs may be used by the Government to guide future contractual efforts, including contracts with other vendors. The use of Internal Research and Development funding (IR&D) is invited, but not required, for consideration of award. If IR&D is proposed, the proposal must clearly specify which portions of the resultant intellectual property and technical output from the proposed effort will be the direct result of funding from this contract versus IR&D. Proposals which include IR&D but which do not clearly make this distinction will not be considered for award. As stated above, the vast majority of what is proposed as output from this contract must be made available to AFRL/SN on a non-proprietary basis. TECHNICAL GOALS The goal of this effort is to develop a new class of compact digital receiver technology tailored to handle the unique challenges of DBF at X-band. The primary emphasis of this effort will be to develop a new digital receiver architectural approach which adds several DBF-specific features and performance capabilities, while leveraging appropriate techniques and capabilities from the existing state-of-the-art of digital receiver technology used for radar and EW systems. DBF-specific capabilities that are of particular interest should include, but are not limited to the following: implementation of digital time delays; implementation of digital sub-banding; and implementation of module-level self-registration features that will allow a DBF Rx module to precisely adjust its timing of digital clock and synchronization signals, phasing of incident RF local oscillator signals, and phasing of RF calibrator pilot tones, injected at the module-level. This program seeks to establish new techniques and design approaches that can be used to implement these and other DBF-specific performance capabilities. These features should be organized into the following four (4) main sub-systems of the DBF Rx: a) RF sub-system, b) digital channelization sub-system, c) digital time delay and filtering sub-system, and d) digital self-registration sub-system. Engineering design trade analyses and design simulation and modeling performance analyses will be used to identify candidate approaches and to simulate the expected performance of all DBF Rx technology developed in this effort. This program also will rigorously demonstrate the validity of the new DBF receiver capabilities by the fabrication and testing of at least four (4), but preferably sixteen (16), prototype DBF receivers at X-band. This program also requires the design, fabrication and testing of a DBF Receiver Test and Evaluation Board, as described in the Technical Approach section of this solicitation. High RF and digital performance is key to the success of this DBF Rx technology research and development program. In an effort to promote new and highly innovative solutions to DBF Rx challenges, a fixed set of technical specifications will not be given for this program. However, the following basic guidelines, which are commensurate with the current state-of-the-art of digital receiver technology, shall serve as performance goals for this program: 1) RF Spurious Free Dynamic Range (SFDR): 72-84 dB; 2) Effective linear digital resolution: 12-14 bits; 3) Noise figure: 2-4 dB; 4) Continuous frequency tuning range: 8-12 GHz; 5) Instantaneous bandwidth: 200-1000 MHz; 6) Maximum length of digital time delays: 4 RF wavelengths at low end of tuning range; 7) Resolution of digital time delays: 0.125 RF wavelengths at high end of tuning range; 8) Digital clock jitter and ADC sampling synchronization: 2-10 picoseconds; 9) Number of digital sub-bands within instantaneous bandwidth: 20-100, of equal width; 10) DC power consumption: 1-5 W; 11) Physical Size: Not to exceed 1 x 4 x 4 inches; 12) Packaging Approach: Modular Tile. In addition to the guidelines given above, significant performance and cost savings advantages may be realized by using COTS components and subsystems, as well as components which were previously developed under IR&D efforts or previously completed contractual programs for the Government. This effort does not seek to develop new electronic components, but does seek to leverage, where practical, available COTS and state-of-the-art components. Although not a requirement for this program, it may also be desirable that the X-band digital receiver technology developed under this effort be applicable to L-band applications, with minor redesign changes, such as changing the LO frequency in the first stage of the RF receiver, or by removal of the first stage of the X-band RF receiver design to yield an L-band design. TECHNICAL APPROACH This technical effort will, first and foremost, include a Concept Development Task where new and innovative DBF Rx functions and implementation techniques are to be developed and integrated with existing capabilities and implementation techniques found in state-of-the-art digital receivers for radar applications. Several candidate approaches should be identified for all major sub-systems of the DBF receiver. For more information on these sub-systems, refer to both the Background and Technical Goals sections of this solicitation. An engineering Trade Space Analysis task will be performed as a major portion of this task, to clearly show the anticipated benefits and weaknesses of the design, as well as technical challenges in development and implementation of the proposed technology. A second task will be the DBF Receiver Design Task. This will include selection of one of the leading design options for each of the DBF Rx sub-systems, as identified in the Concept Development Task. This task will further develop the selected design options and integrate them into a single DBF Rx design, at the point design level. Significant computer modeling and simulation of all RF and digital functions of the selected DBF Rx design will be performed. The output of this task will include both preliminary and critical design reviews, to be held with AFRL/SN. The third task will be the DBF Receiver Implementation Task. The engineering effort of this task will focus on developing and refining the details of achieving physical integration and the functional integration of the selected DBF Receiver point design into fully functioning prototype hardware demonstration deliverables. Packaging, size, weight and power will be issues of great interest. Projections on the cost of producing hundreds to thousands of the DBF Receivers is also of interest. This task will produce between four to sixteen (4 - 16), fully functioning prototype DBF Receivers based on the final design approved by AFRL/SN in the DBF Receiver Design Task. It is critical to make the prototype DBF receivers as identical as possible, and where possible, to use realistic manufacturing and assembly practices that would be typical of limited run initial production (LRIP) fabrication runs. The fourth task will be the DBF Receiver Test and Evaluation Board Task. This task will design, develop, fabricate, and test a separate circuit board which serves as a life-support system to the prototype DBF Receivers. This board must provide LO to the RF sub-system, digital clock and timing synchronization signals to the digital channelization sub-system, and DC-biasing to all sub-systems, and this board must connect to and interface with a laptop computer or PC workstation. All programmable features of the DBF Receiver, including digital filtering, digital time delays, digital sub-banding, etc., must be directly accessible from this board, and must be directly testable using the laptop or workstation. Since data generated by the DBF Rx will be outputted to this board, a large-volume digital data recording medium must be connected to this board, for temporary and permanent storage of output test data. The board must also have an extensive set of test connections, so that all critical points within the RF and digital portions of the DBF Rx module may be injected with appropriate test signals, and so that measurements of the output may be made at all critical points within the DBF Receiver. The fifth task will be DBF Receiver Test and Evaluation. This task will utilize the DBF Receiver Test and Evaluation Board Task to test and demonstrate the performance of all aspects of the prototype DBF receivers. A specific test plan will be developed as part of this task, and must be approved by AFRL/SN. In addition to testing and collection of measured performance data, a significant portion of this task will carefully compare the measured performance vs. the computed simulated performance, modeled in the DBF Receiver Design Task, for all major sub-systems in the DBF Receiver. See Note 26.
- Web Link
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ESC Business Opportunities Web Page
(http://www.herbb.hanscom.af.mil)
- Place of Performance
- Address: N/A
- Zip Code: N/A
- Country: N/A
- Zip Code: N/A
- Record
- SN00234906-W 20030109/030107213427 (fbodaily.com)
- Source
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